Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic functions. In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). A hierarchy of programmable routing resources interconnects the CLBs and IOBs. Loading a configuration bitstream into configuration memory cells of the FPGA customizes these CLBs, IOBs, and programmable routing resources. Additional resources, such as multipliers, processors, memory, and application-specific circuits may also be included.
PLDs are growing ever more dense as vendors attempt to satisfy customer demand for PLDs capable of performing ever more complex tasks. Unfortunately, as die size and complexity increase, so too does the probability of finding a defect on a given die. The process yield therefore decreases with PLD complexity, making already expensive PLDs still more expensive. Yield is expected to approach zero as minimum feature sizes approach molecular dimensions.
PLDs are not design specific, but instead afford users (e.g., circuit designers) the ability to instantiate an almost unlimited number of circuit variations. Not knowing in advance the purpose to which a given PLD will be dedicated places a heavy burden on a PLD vendor to ensure the quality and reliability of the PLD because PLD vendors must verify the functionality of every feature that might be used. As a result, PLD manufacturers discard PLDs' that include even relatively minor defects.
PLD defects can be categorized in two general areas: gross defects that render the entire PLD useless or unreliable, and localized defects that damage a relatively small percentage of the PLD. It has been found that, for large die, close to two thirds of the die on a given wafer may be discarded because of localized defects. Considering the costs associated with manufacturing large integrated circuits, discarding a significant percentage of PLD die has very significant adverse economic impact on PLD manufacturers. This problem is expected to worsen with further reductions in feature size and increases in device complexity.
Others have recognized the growing importance of defect-tolerant reconfigurable systems. For example, in U.S. Pat. No. 5,790,771, incorporated herein, Bruce W. Culbertson and Philip J. Kuekes describe methods that facilitate the use of reconfigurable systems that contain one or more defective resource. That reference discusses techniques for locating and documenting defective resources on reconfigurable systems. Circuit designs are then instantiated on the defective reconfigurable system using the recorded defect information to avoid defective resources.
The main difficulty with the aforementioned “locate and avoid” approach to defect tolerance in reconfigurable systems is that the task of locating defects can be daunting. This difficulty is expected to grow more troublesome with increases in device complexity and with the adoption of nanoscale technology, or “nanotechnology” and molecular-scale technology, or “molectronics.” In the present disclosure, nanotechnology employs device minimum feature sizes that range from about one to ten nanometers, and molectronic devices employ still smaller minimum feature sizes.
Many of the constituent components of devices formed using molectronics or nanotechnology are chemically assembled in a manner that affords process engineers less control over individual circuit features than is currently available in modern photolithography processes. As a result, the super-high density circuits have a far greater number and proportion of defects. PLDs incorporating molectronic and nanotechnology structures are therefore virtually guaranteed to include a significant number of defective resources. There is therefore a need for defect-tolerant methods of instantiating circuit designs on integrated circuits.